The present invention relates to a semiconductor device and to, for example, a semiconductor device that performs a lock step operation which causes a plurality of CPU cores to execute the same process in parallel.
In recent years, as a technique for increasing reliability in semiconductor devices, lock step processors are proposed which cause two central processing unit (CPU) cores to run in the same cycle and execute the same process. Techniques related to such lock step processors are disclosed in Japanese Unexamined Patent Application Publication No. 2012-73828 and United States Patent Publication No. 2008/0244305.
Japanese Unexamined Patent Application Publication No. 2012-73828 discloses an information processing device adopting a lock step system in which CPU modules of a plurality of systems including a processor and a memory with an error detection/correction function perform the same process in clock synchronization. In addition, in the information processing device according to Japanese Unexamined Patent Application Publication No. 2012-73828, a CPU module performs an error correction process by: storing first correction information that is generated when an error is detected from a memory of the system of the CPU module; transmitting the generated first correction information to a CPU module of another system; receiving second correction information that is generated when an error is detected from a memory of the CPU module of the other system; reading first correction information that is stored in a storage unit in accordance with a delay of reception of the second correction information from the CPU module of the other system; and synchronizing the second correction information and the first correction information with each other.
Furthermore, United States Patent Publication No. 2008/0244305 discloses a lock step processor of a delayed lock step system which alleviates timing constraints of a critical path by delaying output from one CPU core using a delay circuit and delaying input to another CPU core using a delay circuit.